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(parent: 30490b1) | patch
plat: intel: Fix faulty DDR calibration value
authorLoh Tien Hock <[email protected]>
Wed, 13 Feb 2019 06:39:31 +0000 (14:39 +0800)
committerLoh Tien Hock <[email protected]>
Wed, 13 Feb 2019 06:39:31 +0000 (14:39 +0800)
commit51f366ac85c22bc2a3a729192acba7cb7a2cbb13
treee12fa2fad5d4aa9b50303788fd52afed2a1bdbb4tree | snapshot
parent30490b15fef50900acac0f23a528651c24759e7dcommit | diff
plat: intel: Fix faulty DDR calibration value

A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.

Signed-off-by: Loh Tien Hock <[email protected]>
plat/intel/soc/stratix10/bl2_plat_setup.c diff | blob | history
plat/intel/soc/stratix10/include/s10_memory_controller.h diff | blob | history
plat/intel/soc/stratix10/soc/s10_memory_controller.c diff | blob | history
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